docs(dn)-Ghala-Buarish-11/30/25 (#442)

Author: Ghqlq

src/design_notebooks/2025fall/gb2789.md

@@ -107,4 +107,11 @@ I keep getting error `CMake Error at CMakeLists.txt:8 (nyu_link_sv):
 
 [Processor-Design VIP Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New folder: Lab3_Ghala
 
-**Discussion:** Even though we wrote a tb during RiSC-16 project, This is my first time writing testbench in C++ for SystemVerilog modules. Some new keywords were "TEST_CASE", "REQUIRE", ".eval", "tick".
+**Discussion:** Even though we wrote a tb during RiSC-16 project, This is my first time writing testbench in C++ for SystemVerilog modules. Some new keywords were "TEST_CASE", "REQUIRE", ".eval", "tick".
+
+## Week12: 11/24/25 - 11/30/25
+- Completed lab 4.
+
+[Processor-Design VIP Project repository](https://github.com/Ghqlq/Processor-Design-Projects) - New folder: Lab4_Ghala
+
+**Discussion:** In this lab I got an intro into the actual verification toolchain. We got to know how different tools (vcpkg, CMake, Catch2, Verilator...) work together to create the verification process. I understood the entire flow, however, I still need more practice to be able to do all this without a guided lab.