diff --git a/src/design_notebooks/2025fall/hd2609.md b/src/design_notebooks/2025fall/hd2609.md index e00e542..8b563bf 100644 --- a/src/design_notebooks/2025fall/hd2609.md +++ b/src/design_notebooks/2025fall/hd2609.md @@ -100,3 +100,21 @@ Summary: This week I spent most of the time testing the code and understanding c * I also finsihed reading lab 7. It is about The RISC-V ISA specifications. I did not go deeper of that. It seems it is similar to ARM or x86. They are all instruction set architecture, but RISC-V is open-source. If I have time, I would like to know more about RISC-V ISA and maybe find a project to work on in the future. Summary: I completed all current avaliable labs now. I talked to Darren and would like to challenge myself to finish RiSC-16 chip project on my own because I did program counter and register files last semester. Now, with more knowledge about Verilog, I could try finish other parts. If given time, I will try develop testbench code or ask leader for it. + +## Week of November 23th + +### Project Work + +* Did more Verilog practice questions on the HDLBits. I finished until "Reduction Operators" problem. +* I reviewed document on RiSC-16 chip project, but have not looked at my unfinished code yet. + +Summary: I contact with Darren and confirmed that I could work on the RiSC-16 chip project last week. I did not make a lot progress due to ThanksGiving break. Also, I receive the task that we need to make a presentation about what we learnt this semester. I will prepare sldies about my debug on Github version and research on AI generating high quality Verilog code. + +## Week of November 30th + +### Project Work + +* Did more Verilog practice questions on the HDLBits. I finished until "Combinational for-loop: vector reversal 2" problem. +* I did presentation on 6th, December. + +Summary: I spent a lot time on reading papers of the topic I chose. I created slides and successfully did the presentation. This week, I spent a lot of time on other courses because I have three exams next week.