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Fix fifo depths, improve simulation #28

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Fix fifo depths, improve simulation #28

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8b2f51a
Set Hyperram chips conf register in tb
phsauter Nov 29, 2024
3bcf35c
Remove unused parameters
phsauter Oct 28, 2025
9a86747
Fix fifo depth for clk_sys=clk_phy
phsauter Oct 28, 2025
04462ee
Add vsim outputs and model to gitignore
phsauter Oct 28, 2025
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7 changes: 6 additions & 1 deletion .gitignore
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Original file line number Diff line number Diff line change
@@ -1,3 +1,8 @@
.bender
scripts/compile.tcl
models/s27ks0641
axi_log/
work/
transcript
modelsim.ini
vsim.wlf
models/s27ks0641
1 change: 1 addition & 0 deletions Bender.yml
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Expand Up @@ -47,5 +47,6 @@ sources:
- test/fixture_hyperbus.sv
- test/hyperbus_tb.sv
- test/dut_if.sv
- test/hyperbus_tb_pkg.sv
- test/axi_hyper_tb.sv
- src/hyperbus.sv
5 changes: 2 additions & 3 deletions src/hyperbus.sv
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Expand Up @@ -28,13 +28,12 @@ module hyperbus #(
parameter type reg_rsp_t = logic,
parameter type axi_rule_t = logic,
// The below have sensible defaults, but should be set on integration!
parameter int unsigned RxFifoLogDepth = 2,
parameter int unsigned TxFifoLogDepth = 2,
parameter int unsigned RxFifoLogDepth = 3,
parameter int unsigned TxFifoLogDepth = 3,
parameter logic [RegDataWidth-1:0] RstChipBase = 'h0, // Base address for all chips
parameter logic [RegDataWidth-1:0] RstChipSpace = 'h1_0000, // 64 KiB: Current maximum HyperBus device size
parameter hyperbus_pkg::hyper_cfg_t RstCfg = hyperbus_pkg::gen_RstCfg(NumPhys,MinFreqMHz),
parameter int unsigned PhyStartupCycles = 300 * 200, /* us*MHz */ // Conservative maximum frequency estimate
parameter int unsigned AxiLogDepth = 3,
parameter int unsigned SyncStages = 2
) (
input logic clk_phy_i,
Expand Down
106 changes: 52 additions & 54 deletions src/hyperbus_phy_if.sv
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Expand Up @@ -8,10 +8,8 @@ module hyperbus_phy_if import hyperbus_pkg::*; #(
parameter int unsigned IsClockODelayed = 1,
parameter int unsigned NumChips = 2,
parameter int unsigned NumPhys = 2,
parameter int unsigned TimerWidth = 16,
parameter int unsigned RxFifoLogDepth = 3,
parameter int unsigned StartupCycles = 60000, /*MHz*/ // Conservative maximum frequency estimate
parameter int unsigned SyncStages = 2,
parameter int unsigned SyncStages = 2,
parameter type hyper_tx_t = logic,
parameter type hyper_rx_t = logic
)(
Expand Down Expand Up @@ -61,11 +59,11 @@ module hyperbus_phy_if import hyperbus_pkg::*; #(

logic [NumPhys-1:0][1:0] fifo_axi_usage;

logic tx_both_ready, ts_both_ready;
logic rx_both_valid, b_both_valid;
logic tx_both_ready, ts_both_ready;
logic rx_both_valid, b_both_valid;

logic [NumPhys-1:0] phy_tx_ready;
logic phy_tx_valid;
logic [NumPhys-1:0] phy_tx_ready;
logic phy_tx_valid;

logic [NumPhys-1:0] phy_trans_ready;
logic [NumPhys-1:0] phy_trans_valid;
Expand All @@ -77,7 +75,7 @@ module hyperbus_phy_if import hyperbus_pkg::*; #(
genvar i;
generate

if (NumPhys==2) begin : phy_wrap
if (NumPhys==2) begin : phy_wrap

logic [NumPhys-1:0] phy_enable;
logic [NumPhys-1:0] phy_busy;
Expand Down Expand Up @@ -156,41 +154,41 @@ module hyperbus_phy_if import hyperbus_pkg::*; #(

.busy_o ( phy_busy[i] ),

.rx_data_o ( phy_fifo_rx[i].data ),
.rx_last_o ( phy_fifo_rx[i].last ),
.rx_error_o ( phy_fifo_rx[i].error ),
.rx_valid_o ( phy_fifo_valid[i] ),
.rx_ready_i ( phy_fifo_ready[i] ),
.rx_data_o ( phy_fifo_rx[i].data ),
.rx_last_o ( phy_fifo_rx[i].last ),
.rx_error_o ( phy_fifo_rx[i].error ),
.rx_valid_o ( phy_fifo_valid[i] ),
.rx_ready_i ( phy_fifo_ready[i] ),

.tx_data_i ( tx_i.data[16*i +:16] ),
.tx_strb_i ( tx_i.strb[2*i +:2] ),
.tx_last_i ( tx_i.last ),
.tx_valid_i ( phy_tx_valid ),
.tx_ready_o ( phy_tx_ready[i] ),
.tx_data_i ( tx_i.data[16*i +:16] ),
.tx_strb_i ( tx_i.strb[2*i +:2] ),
.tx_last_i ( tx_i.last ),
.tx_valid_i ( phy_tx_valid ),
.tx_ready_o ( phy_tx_ready[i] ),

.b_error_o ( phy_b_error[i] ),
.b_valid_o ( phy_b_valid[i] ),
.b_ready_i ( phy_b_ready ),
.b_error_o ( phy_b_error[i] ),
.b_valid_o ( phy_b_valid[i] ),
.b_ready_i ( phy_b_ready ),

.trans_i ( trans_i ),
.trans_cs_i ( trans_cs_i ),
.trans_valid_i ( phy_trans_valid[i] ),
.trans_ready_o ( phy_trans_ready[i] ),

.hyper_cs_no ( hyper_cs_no[i] ),
.hyper_ck_o ( hyper_ck_o[i] ),
.hyper_ck_no ( hyper_ck_no[i] ),
.hyper_rwds_o ( hyper_rwds_o[i] ),
.hyper_rwds_i ( hyper_rwds_i[i] ),
.hyper_rwds_oe_o( hyper_rwds_oe_o[i] ),
.hyper_dq_i ( hyper_dq_i[i] ),
.hyper_dq_o ( hyper_dq_o[i] ),
.hyper_dq_oe_o ( hyper_dq_oe_o[i] ),
.hyper_reset_no ( hyper_reset_no[i] )
);
.hyper_cs_no ( hyper_cs_no[i] ),
.hyper_ck_o ( hyper_ck_o[i] ),
.hyper_ck_no ( hyper_ck_no[i] ),
.hyper_rwds_o ( hyper_rwds_o[i] ),
.hyper_rwds_i ( hyper_rwds_i[i] ),
.hyper_rwds_oe_o( hyper_rwds_oe_o[i] ),
.hyper_dq_i ( hyper_dq_i[i] ),
.hyper_dq_o ( hyper_dq_o[i] ),
.hyper_dq_oe_o ( hyper_dq_oe_o[i] ),
.hyper_reset_no ( hyper_reset_no[i] )
);

end // for ( i=0; i<NumPhys;i++)
end else begin // if (NumPhys==2)
end // for ( i=0; i<NumPhys;i++)
end else begin // if (NumPhys==2)

hyperbus_phy #(
.IsClockODelayed( IsClockODelayed ),
Expand All @@ -208,26 +206,26 @@ module hyperbus_phy_if import hyperbus_pkg::*; #(

.busy_o ( ),

.rx_data_o ( rx_o.data ),
.rx_last_o ( rx_o.last ),
.rx_error_o ( rx_o.error ),
.rx_valid_o ( rx_valid_o ),
.rx_ready_i ( rx_ready_i ),

.tx_data_i ( tx_i.data ),
.tx_strb_i ( tx_i.strb ),
.tx_last_i ( tx_i.last ),
.tx_valid_i ( tx_valid_i ),
.tx_ready_o ( tx_ready_o ),

.b_error_o ( b_error_o ),
.b_valid_o ( b_valid_o ),
.b_ready_i ( b_ready_i ),

.trans_i ( trans_i ),
.trans_cs_i ( trans_cs_i ),
.trans_valid_i ( trans_valid_i ),
.trans_ready_o ( trans_ready_o ),
.rx_data_o ( rx_o.data ),
.rx_last_o ( rx_o.last ),
.rx_error_o ( rx_o.error ),
.rx_valid_o ( rx_valid_o ),
.rx_ready_i ( rx_ready_i ),

.tx_data_i ( tx_i.data ),
.tx_strb_i ( tx_i.strb ),
.tx_last_i ( tx_i.last ),
.tx_valid_i ( tx_valid_i ),
.tx_ready_o ( tx_ready_o ),

.b_error_o ( b_error_o ),
.b_valid_o ( b_valid_o ),
.b_ready_i ( b_ready_i ),

.trans_i ( trans_i ),
.trans_cs_i ( trans_cs_i ),
.trans_valid_i ( trans_valid_i ),
.trans_ready_o ( trans_ready_o ),

.hyper_cs_no ( hyper_cs_no ),
.hyper_ck_o ( hyper_ck_o ),
Expand Down
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